1. Field of the Invention
Embodiments of the invention relate to phase detectors, and more particularly, in one or more embodiments, to digital phase detectors.
2. Description of the Related Art
Phase detectors serve to detect a phase difference between two signals. Phase detectors have wide applications in various electronic devices. Phase detectors are often used for high-speed electronic devices, such as synchronous DRAM. Phase detectors are often part of phase-locked loop (PLL) systems or delay-locked loop (DLL) systems.
FIG. 1 illustrates a conventional digital phase detector 100. The phase detector 100 is configured to detect which one of two clock signals is leading the other. The phase detector 100 includes a phase detection circuit 101 and an output circuit 102. The phase detection circuit 101 can be implemented with a first RS latch 110 configured to receive two clock signals clkA, clkB, and detect which clock signal is leading or lagging the other. The output circuit 102 can be implemented with a second RS latch 120 configured to maintain the outputs from the phase detection circuit and provide an output signal indicative of which clock signal is leading. The first and second RS latches 110, 120 can be connected to form cascaded RS latches.
The first RS latch 110 includes a first NAND gate 111 and a second NAND gate 112, which are cross-coupled to generate positive feedback. The first NAND gate 111 has a first input 111a, a second input 111b, and an output d1. The second NAND gate 112 has a first input 112a, a second input 112b, and an output u1. The first input 111a of the first NAND gate 111 receives a first clock signal clkA. The second input 111b of the first NAND gate 111 receives the output signal u1 from the second NAND gate 112. The first input 112a of the second NAND gate 112 receives the output signal d1 from the first NAND gate 111. The second input 112b of the second NAND gate 112 receives a second clock signal clkB.
The second RS latch 120 includes a third NAND gate 121 and a fourth NAND gate 122 cross-coupled with each other. The third NAND gate 121 has a first input 121a, a second input 121b, and an output up1. The fourth NAND gate 122 has a first input 122a, a second input 122b, and an output 122c. The first input 121a of the third NAND gate 121 receives the output signal d1 from the first NAND gate 111 of the first RS latch 110. The second input 121b of the third NAND gate 111 receives the output signal 122c from the fourth NAND gate 122. The first input 122a of the fourth NAND gate 122 receives the output signal up1 from the third NAND gate 121. The second input 122b of the fourth NAND gate 122 receives the output signal u1 from the second NAND gate 112 of the first RS latch 110.
With reference to FIGS. 1 and 2, the operation of the conventional phase detector 100 will be described. The illustrated phase detector 100 performs phase detection for rising edges of the first and second clock signals clkA, clkB. Initially, both of the inputs 111a, 112b of the first RS latch 110 are low, and thus both of the outputs d1, u1 thereof are high. When one of the clock signals clkA, clkB rises prior to the other, the output of the NAND gate 111 or 112 receiving the leading clock signal falls first. This in turn feeds back to the input of the other NAND gate, forcing its output to remain high, regardless of whether the other clock signal rises thereafter. Thus, the state of the outputs d1, u1 can indicate which one of the two clock signals leads the other. Then, when the leading clock signal falls, the output of the NAND gate receiving the leading clock signal rises, thereby preparing the first RS latch 110 for another phase detection. Before phase detection, the phase detector 100 should pre-charge the outputs d1, u1 of the phase detection circuit 101 to substantially the same voltage level because phase detection depends on which one of the outputs d1, u1 of the first RS latch 110 goes low first.
In the illustrated timing diagram of FIG. 2, during pre-charging periods, both the first and second clock signals clkA, clkB are low (L). In the timing diagram, the horizontal axis represents time which increases to the right. Because the clock signal inputs clkA, clkB to the NAND gates 111, 112 are low, the outputs d1, u1 of the first RS latch 110 are pre-charged to a high (H) level (e.g., the power supply voltage level Vcc of the NAND gates 111, 112). During the pre-charging periods, the output up1 of the third NAND gate 121 is either high or low, depending on the previous phase detection result.
When one of the NAND gates 111, 112 receives a clock signal clkA or clkB leading the other, that NAND gate outputs a low while the other NAND gate outputs a high. In the illustrated timing diagram of FIG. 2, the first clock signal clkA starts rising at time t1, leading the rising of the second clock signal clkB. When the first clock signal clkA goes beyond a certain voltage threshold, the output d1 of the first NAND gate 111 starts falling. The second clock signal clkB starts rising at time t2. In the illustrated timing diagram, time t2 occurs soon after time t1, before the output d1 has transitioned. Similar to the operation of the output d1 of the first NAND gate 111, when the second clock signal clkB transitions beyond a certain voltage threshold, the output signal u1 of the second NAND gate 112 starts falling (assuming that the output 112a is still high). However, at time t3, the output signal d1 of the first NAND gate 111 goes low first, and maintains the output signal u1 of the second NAND gate 112 high.
The second RS latch 120 receives the output signals d1, u1 from the first RS latch 110, and changes its output depending on the output signals d1, u1. In the illustrated timing diagram, the output signal d1 of the first NAND gate 111 goes low whereas the output signal u1 of the second NAND gate 112 is kept high. The third NAND gate 121 outputs a high signal because d1 is low. The fourth NAND gate 122 outputs a low signal because both inputs to the fourth NAND gate 122 are high. The output up1 of the third NAND gate 121 is high to indicate that the first clock signal clkA leads the second clock signal clkB. On the other hand, if the second clock signal clkB leads the first clock signal clkA, the output up1 of the third NAND gate 121 is low to provide the phase detection indication.
In certain devices, the phase detector 100 can be used for high frequency clock signals. In such cases, the higher the frequency is, the shorter a period of time for which both the first and second clock signal clkA, clkB are low. If the period is shorter than the time needed for sufficiently pre-charging both outputs d1, u1 to the same voltage level, the phase detection results may not be reliable. Therefore, there is a need to provide a phase detector that can operate reliably at relatively high frequencies.